Semiconductor integrated circuit device

ABSTRACT

A semiconductor integrated circuit device includes a logic circuit to perform a predetermined process, a clock generator to supply a clock signal to the logic circuit, and a speed controller to control the operation speed of the logic circuit. The clock generator changes the frequency of the clock signal by a frequency control signal during a time when the logic circuit is operating, and the speed controller controls the operating speed of the logic circuit in accordance with a change in the clock signal.

[0001] This is a continuation-in-part application of patent applicationSer. No. 08/622,389 (Mar. 27, 1996) in the United States and contains apart of that disclosure.

TECHNICAL FIELD

[0002] The present invention relates to a semiconductor integratedcircuit, and, more particularly, a semiconductor integrated circuitdevice suitable for high-speed operation.

BACKGROUND ART

[0003] In an integrated circuit using CMOS transistors, characteristicsfluctuation exists due to variations in transistor dimension caused by afabrication process and a change in the environment, such as temperatureor supply voltage, during operation.

[0004] As described in “1994 symposium on VLSI technology digest oftechnical papers” (June, 1994), pp. 13 to 14, as an MOS transistorbecomes finer, fluctuation in basic parameters, such as a thresholdvalue due to the characteristics fluctuation caused by a fabricationprocess, becomes larger.

[0005]FIG. 12 schematically shows delay of a CMOS circuit with respectto the device feature size of a MOS transistor and the range ofvariation. In designing a CMOS integrated circuit, the worst delay inFIG. 12 has to be considered. By an increase in the range of variation,even if the device becomes finer, high-speed operation is limited by theworst delay. If the delay of the CMOS circuit can be made “typical” or“best” by suppressing the characteristics fluctuation, the highprocessing speed of the circuit can be promoted.

[0006] As a method of suppressing the characteristics fluctuation byimproving the circuit, in Nikkei Electronics 7-28 (1997), pp. 113 to126, a technique is described as follows: A leakage current of a monitoris measured and a substrate bias is changed so that the current becomesa constant value. Delay of a replica is also measured. A change in delayis detected, and the supply voltage is changed, thereby suppressing thecharacteristics fluctuation.

[0007] According to the technique described in Nikkei Electronics 7-28(1997), pp. 113 to 126, the substrate bias is controlled so that theleakage current of the MOS transistor when the gate voltage is 0Vbecomes a constant value. Since the leakage current of the MOStransistor increases as the temperature rises, the threshold has to beincreased by applying the substrate bias. In this case, there is adrawback such that the ON current of the MOS transistor conspicuouslydecreases by deterioration in mobility and increase in the threshold dueto the temperature rise, and as a result, the processing speed of thecircuit decreases. A filter having an inductance and a capacitance isformed outside of the chip and used to generate a supply voltage fordelay control. Since it takes a few μ seconds until an output voltage ofthe filter is stabilized, stabilization time of a control signal islong, and the signal tends to be unstable. Consequently, controlaccuracy cannot be raised. When the capacitance and the inductance usedfor the filter are formed on the same chip on which a circuit to becontrolled is also mounted, the fact that they occupy a large areabecomes a problem.

[0008] Japanese Unexamined Patent Application No. 4-247653 discloses aconcept such that a delay detector is provided to suppress delayvariations of a gate circuit and the substrate bias of the gate circuitis controlled on the basis of the detection result.

[0009] Japanese Unexamined Patent Application No. 5-152935 alsodiscloses a concept such that the substrate bias is controlled by usinga capacitive filter and a charge pump to suppress device variations,thereby improving the yield.

[0010] Further, Japanese Unexanmined Patent Application No. 8-274620discloses a concept such that the delay amount of a circuit is detectedby using a reference clock sisal and the substrate bias of the circuitis controlled on the basis of the detection result.

DISCLOSURE OF INVENTION

[0011] It is an object of the invention to solve the problems of theconventional techniques.

[0012] More specifically, the inventors of the present invention haveexamined the problems in detail, which may occur when the conventionaltechniques are applied to a real semiconductor integrated circuitdevice, and propose the present invention. The present invention is toprovide a semiconductor integrated circuit constructed by an MOS (MIS)transistor, in which characteristics fluctuation of a CMOS circuit issuppressed in short stabilization time and in a small area to therebyraise the control accuracy and improve the operating speed of the maincircuit.

[0013] In order to achieve the subject, a semiconductor integratedcircuit device as a representative embodiment of the invention includesa logic circuit for performing a predetermined process and asubstrate-bias controller for supplying a substrate bias to an MIStransistor constructing the logic circuit. The logic circuit takes theform of an MIS transistor, and the substrate-bias controller supplies asuitable substrate bias to the MIS transistor in accordance with thecharacteristics fluctuation of the logic circuit. The threshold of theMIS transistor is changed by changing the substrate bias and thecharacteristics fluctuation of the logic circuit is suppressed. Thecharacteristic of the logic circuit is detected as a delay, and theamount of change of the delay is converted into a digital amount. As aresult, the substrate-bias controller can be constructed by a digitalcircuit, so that the stabilization time of the control voltage isshortened and the circuit scale is reduced.

[0014] A typical construction example of the invention is asemiconductor integrated circuit device including: a logic circuit forperforming a predetermined process; a digital-to-analog converter forgenerating a substrate bias for controlling a threshold of an MIStransistor constricting the logic circuit; a voltage-controlled circuitfor outputting a control signal in accordance with a delay signal; and adelay detector which can vary operating speed, characterized in that thedelay detector receives a clock signal supplied from the outside andoutputs a delay signal. The voltage-controlled circuit receives thedelay signal of the delay detector and outputs a control signalaccording to delay time. The digital-to-analog converter receives thecontrol signal supplied from the voltage-controlled circuit andgenerates a voltage according to the control signal, and the operatingspeed of the logic circuit and the delay detector is controlled byvoltage supplied from the digital-to-analog converter.

[0015] In the example, since the main part of the controller deals witha digital signal, the circuit configuration is simple. The controllerpart and the circuit to be controlled can also be formed on differentchips.

[0016] As a typical example of the circuits, the delay detector iscomprised of a clock-duty modulator and a delay monitoring circuit. Thevoltage-controlled circuit is constructed by a delay comparator, thedigital-to-analog converter is constructed by a substrate-biasgenerator, and the clock-duty modulator receives the clock signal fromthe outside and outputs a clock signal of an arbitrary clock duty ratio.

[0017] As another example, the delay monitoring circuit outputs anoutput signal of the clock-duty modulator with a predetermined delay.The delay comparator obtains a delay difference between the outputsignal of the clock-duty modulator and the output signal of the delaymonitoring circuit by comparison, and outputs a signal according to thedifference. The substrate-bias generator generates a substrate biasaccording to the output signal of the delay comparator, and the delay inboth the logic circuit and the delay monitoring circuit is controlled bythe substrate bias generated by the substrate-bias generator.

[0018] As another typical example, the delay detector is comprised of adivider and an oscillator, the voltage-controlled circuit is comprisedof a phase-frequency detector and a phase-frequency controller, and thedigital-to-analog converter is constructed by a voltage generator. Theclock signal from the outside is supplied to the divider by which thefrequency of the clock signal is optionally divided, the phase-frequencydetector compares a phase and a frequency of a frequency-division signalof the divider with those of an output signal of the oscillator andproduces an output signal according to the difference. Thephase-frequency controller outputs a control signal in accordance withan output signal of the phasefrequency detector, the voltage generatorgenerates a substrate bias in accordance with the control signal of thephase-frequency controller, and the operating speed of both the logiccircuit and the oscillator is controlled by the substrate bias generatedby the voltage generator.

[0019] Further, as a preferable example, a pMOS circuit and an nMOScircuit are separately controlled.

[0020] More specifically, the delay detector is comprised of a pMOSdelay detector for detecting a change in the threshold of a pMOStransistor and an nMOS delay detector for detecting a change in thethreshold of an nMOS transistor. Two voltage-controlled circuits and twodigital-to-analog converters are prepared for the pMOS transistor andthe nMOS transistor. The operating speed of the pMOS delay detector iscontrolled by a substrate bias for the pMOS transistor generated by thedigital-to-analog converter for the pMOS transistor, and the operatingspeed of the nMOS delay circuit is controlled by the substrate bias forthe nMOS transistor generated by the digital-to-analog converter for thenMOS transistor.

[0021] In the invention, by controlling the substrate bias of thetransistor constructing the circuit, the threshold of the transistor iscontrolled, thereby controlling the operating speed of the circuit. Inthis case, when the threshold of the transistor decreases, what iscalled a subthreshold leakage current (leakage current between the gateand the source) increases. When the leakage current increases, thetemperature of the circuit rises and the delay of the circuit increases.

[0022] In the case of decreasing the threshold of the transistorconstructing the circuit to reduce the delay when the delay of thecircuit is detected and increased, if no limiter is provided, thesubstrate bias is continuously applied in the direction of decreasingthe threshold, so that there is a danger that an operating error in hightemperature occurs.

[0023] According to the invention, there is consequently proposed asemiconductor integrated circuit device comprising a circuit to becontrolled including at least one transistor, and a controller forcontrolling a substrate bias of the transistor in the circuit to becontrolled, for changing the threshold of the transistor, wherein thecontroller has a limiter for controlling the substrate bias within apredetermined range.

[0024] As an example, the limiter has a leakage current detector fordetecting leakage current of the transistor. When the leakage currentincreases to a predetermined value or larger, the substrate bias controlof the controller is stopped.

[0025] In the case where the digital-to-analog converter for generatingthe substrate bias to control the threshold of the MIS transistorconstructing the logic circuit is used, when the leakage current isincreased to a predetermined value or larger, an output voltage of thedigital-to-analog converter is fixed, thereby enabling the increase inthe leakage current to be limited.

[0026] Further, in the invention, a detailed sequence to control thesubstrate bias is provided.

[0027] Specifically, in the invention, there is proposed a circuitdevice including a circuit to be controlled including a transistor and acontroller for dynamically controlling a substrate bias of thetransistor, characterized in that the circuit device performs operationsin the following order:

[0028] (1) setting of the substrate bias of the transistor to apredetermined value,

[0029] (2) application of a supply voltage to the transistor, and

[0030] (3) dynamirc control of the substrate bias of the transistor.

[0031] In this case, the controller can comprise a monitoring circuitfor monitoring delay in the controlled circuit and a substrate-biasgenerator for controlling the substrate bias of the transistor on thebasis of a signal from the monitoring circuit.

[0032] More specifically, there is provided a semiconductor integratedcircuit device comprising a logic circuit for performing a predeterminedprocess, two voltage stabilizers, a control voltage stable-statedetector, a reset cancellation circuit, and an operation/non-operationswitching circuit, characterized in that the substrate bias is suppliedafter the device is started. The first voltage stabilizer supplies asupply voltage after the substrate bias becomes stable, the secondvoltage stabilizer supplies a control signal to the semiconductorintegrated circuit after the supply voltage becomes stable, and thecontrol voltage stable-state detector detects the stable state of anoutput voltage for control of the semiconductor integrated circuit. Thereset cancellation circuit sends a reset cancellation signal to thelogic circuit when the control voltage stable-state detector detects thestable state to thereby cancel the reset state of the logic circuit andto allow the operation to start, and the operation/non-operationswitching circuit switches validity/invalidity of the control of thesemiconductor integrated circuit in accordance with theoperation/non-operation switching signal, thereby preventing anerroneous operation of the logic circuit at the time of start-up orduring operation.

[0033] In association with the increase in the functions of theintegrated circuit device, there is a case such that it is effective todivide the circuit into a plurality of blocks and change the operatingspeed and the operating voltage block by block.

[0034] According to another mode of the invention, there is provided asemiconductor integrated circuit device comprising a logic circuithaving at least first and second blocks, first and second speedcontrollers, and a clock generator, characterized in that differentsupply voltages are supplied to the first and second blocks, and thefirst and second speed controllers control the operating speeds of thelogic circuit in the blocks in accordance with the supply voltagesapplied to the respective blocks.

[0035] As another mode of the invention with emphasis on reducing thepower consumption of the circuit, there is provided a semiconductorintegrated circuit device comprising a first circuit block to becontrolled and a second circuit block to be controlled, characterized inthat each of the circuits to be controlled is provided with a switch,and the supply of power to a transistor included in each of the circuitsto be controlled is controlled by the switch. Each of the circuits to becontrolled is provided with a controller, and the substrate bias of thetransistor included in each of the circuits to be controlled iscontrolled by the controller.

[0036] The switch is controlled by, for example, a mode switchingsignal. By turning off the switch when the circuit is not operating, theleakage current of the FET in the circuit can be reduced. When thecircuit is operating, the threshold of the FET is controlled by adynamiuc control of the substrate bias of the transistor as describedabove, and the operating speed and the power consumption of the circuitcan be set to proper values. For example, the controller detects thedelay of the circuit to be controlled and controls the substrate bias ofthe transistor on the basis of the detection result.

[0037] It is also possible to apply different supply voltages to thecircuits to be controlled.

[0038] As a layout of the circuit, the speed controller is comprised ofthe delay detector and the controller. When the delay detector isdisposed in the block to be controlled, particularly, in the center ofthe block, the operating speed can be accurately detected.

[0039] As another mode of the invention, there is provided asemirconductor integrated circuit device comprising a logic circuit forperforming a predetermined process, an input/output circuit fortransmitting a signal to the logic circuit, and a speed controller forcontrolling the operating speed of the circuit, characterized in thatthe signal transmitting speed of the input/output circuit is controlledby the speed controller. Specifically, the speed controller controls thesubstrate bias of the transistor constructing the input/output circuitto change the threshold, thereby controlling the operating speed.

[0040] As another example, there is provided a semiconductor integratedcircuit device comprising a logic circuit for performing a predeterminedprocess, a clock generator for supplying a clock signal to the logiccircuit, and a speed controller for controlling the operation speed ofthe circuit, characterized in that the clock generator changes thefrequency of the clock signal by a frequency control signal while thelogic circuit is operating, and the speed controller controls theoperating speed of the logic circuit in accordance with a change in theclock signal.

[0041] There is also provided a senmconductor integrated circuit-devicecomprising a logic circuit having at least first and second blocks,first and second speed controllers, and a clock generator, characterizedin that clock signals of different frequencies are supplied to the firstand second blocks, and the first and second speed controllers controlthe operating speeds of the logic circuit in the blocks in accordancewith the frequencies of the clock signals supplied to the respectiveblocks.

BRIEF DESCRIPTION OF DRAWINGS

[0042]FIG. 1 is a diagram showing the configuration of a firstembodiment of the invention.

[0043]FIG. 2 is a diagram showing the detailed configuration of theembodiment of the invention.

[0044]FIG. 3 is a diagram of a clock-duty modulator.

[0045]FIG. 4 is an output waveform chart of the clock-duty modulator.

[0046]FIG. 5 is diagram of a delay monitoring circuit.

[0047]FIG. 6 is a diagram of a delay comparator.

[0048]FIG. 7 is a diagram of a substrate-bias generator.

[0049]FIG. 8 is a diagram of a selector.

[0050]FIG. 9 is a diagram of a selector.

[0051]FIG. 10 is a diagram of a lock detector.

[0052]FIG. 11 is a diagram of a standby circuit.

[0053]FIG. 12 is a diagram showing the relation between device featuresize and gate delay.

[0054]FIG. 13 is a diagram showing the relation between the substratebias and the threshold voltage.

[0055]FIG. 14 is a diagram showing the relation between the substratebias and the threshold voltage.

[0056]FIG. 15 is a diagram showing the relation between the substratebias and gate delay.

[0057]FIG. 16 is a diagram showing the configuration of anotherembodiment of the invention.

[0058]FIG. 17 is a diagram showing the configuration of anotherembodiment of the invention.

[0059]FIG. 18 is a diagram showing the configuration of anotherembodiment of the invention.

[0060]FIG. 19 shows a digital-to-analog converter.

[0061]FIG. 20 is a diagram showing the relation between threshold andleakage current.

[0062]FIG. 21 is a diagram showing the configuration of anotherembodiment of the invention.

[0063]FIG. 22 is a diagram showing the configuration of anotherembodiment of the invention.

[0064]FIG. 23 is a diagram of a divider.

[0065]FIG. 24 is a diagram of a threshold-voltage controlled oscillator.

[0066]FIG. 25 is a diagram of a threshold-voltage controlled oscillator.

[0067]FIG. 26 is a diagram of a threshold-voltage controlled oscillator.

[0068]FIG. 27 is a diagram of a threshold-voltage controlled delay linecircuit.

[0069]FIG. 28 is a diagram of a threshold-voltage controlled delay linecircuit.

[0070]FIG. 29 is a diagram of a phase-frequency detector.

[0071]FIG. 30 is a diagram of a phase-frequency controller.

[0072]FIG. 31 is a circuit diagram of an up-down counter.

[0073]FIG. 32 is a circuit diagram of a half adder.

[0074]FIG. 33 is a circuit diagram of a full adder.

[0075]FIG. 34 is a circuit diagram of a decoder.

[0076]FIG. 35 is a diagram of a voltage generator.

[0077]FIG. 36 is a diagram showing the configuration of anotherembodiment of the invention.

[0078]FIG. 37 is a diagram of an operating amplifier.

[0079]FIG. 38 is a diagram of an operating amplifier.

[0080]FIG. 39 is a diagram showing the configuration of anotherembodiment of the invention.

[0081]FIG. 40 is a diagram of a delay detector.

[0082]FIG. 41 is a diagram of a delay detector.

[0083]FIG. 42 is a diagram of a delay detector.

[0084]FIG. 43 is a diagram of a delay detector.

[0085]FIG. 44 is a diagram showing the configuration of anotherembodiment of the invention.

[0086]FIG. 45 is a diagram showing the configuration of anotherembodiment of the invention.

[0087]FIG. 46 is a diagram of a leakage-current detector.

[0088]FIG. 47 is a diagram showing effects of the invention.

[0089]FIG. 48 is a diagram showing effects of the invention.

[0090]FIG. 49 is a diagram showing effects of the invention.

[0091]FIG. 50 is a diagram showing the relation between substrate biasand gate delay.

[0092]FIG. 51 is a diagram showing the configuration of anotherembodiment of the invention.

[0093]FIG. 52 is a diagram of a substrate-bias stable-state detector.

[0094]FIG. 53 is a diagram of a supply-voltage stable-state detector.

[0095]FIG. 54 is a diagram of a lock detector.

[0096]FIG. 55 is a diagram of a reset cancellation circuit.

[0097]FIG. 56 is a diagram showing an operating procedure of theinvention.

[0098]FIG. 57 is a diagram showing an operating procedure of theinvention.

[0099]FIG. 58 is a diagram showing the configuration of anotherembodiment of the invention.

[0100]FIG. 59 is a diagram showing the configuration of anotherembodiment of the invention.

[0101]FIG. 60 is a diagram showing the relation between examples ofapplying the invention and required performances.

[0102]FIG. 61 is a diagram showing the configuration of anotherembodiment of the invention.

[0103]FIG. 62 is a diagram showing the configuration of anotherembodiment of the invention.

[0104]FIG. 63 is a diagram showing the configuration of anotherembodiment of the invention.

[0105]FIG. 64 is a diagram showing the configuration of anotherembodiment of the invention.

[0106]FIG. 65 is a diagram illustrating an example of the configurationof a microprocessor.

[0107]FIG. 66 is a diagram showing the configuration of anotherembodiment of the invention.

BEST MODE FOR CARRYING OUT THE INVENTION

[0108] Embodiments of the invention will be described hereinbelow withreference to the drawings.

[0109]FIG. 1 is a diagram showing the fundamental concept of theinvention. A main circuit LOG transmits a detected signal sig accordingto the operating speed of the circuit to a substrate-bias controllerCNT. The substrate-bias controller CNT supplies both a substrate viasvbp for a p-channel type MOSFET and a substrate vias vbn for ann-channel type MOSFET to the main circuit LOG. The main circuit LOG isconstructed by an MOS transistor. By controlling the substrate bias ofthe MOS transistor, a threshold voltage is controlled.

[0110] With such a construction, even when the characteristics of theMOS transistor fluctuate, due to variations in temperature and supplyvoltage or variations in the fabrication process of the MOS transistor,by controlling the substrate bias to control the threshold voltage ofthe MOS transistor, the operating speed can be made always constant.Further, the MOS transistor is fabricated so that it's threshold ispreliminarily set to be lower than the limit value determined by adesired maximum leakage current, and the operating speed of the maincircuit is controlled to be constant by the substrate bias control,thereby enabling substantial high speed processing to be realized. Withsuch a construction, when the main circuit is in a suspended mode, theleakage current is reduced by increasing the threshold of the maincircuit, thereby enabling the power consumption to be reduced.

[0111]FIG. 20 shows the relation between the threshold of the MOStransistor and the leakage current. In a standard MOS transistor, it isdesigned with the threshold at point A and the range of variation causedby a process or the like does not exceed the desired limit of a leakagecurrent. In the invention, by decreasing the threshold to point B andapplying the substrate bias, even when the threshold changes, the rangeof variation does not exceed the limit of leakage current.

[0112]FIG. 16 is a diagram showing another embodiment of the invention.A main circuit LOG10 receives a clock signal clk10 from the outside andgenerates a detected signal sig10 in accordance with the operationfrequency of the clock. A substrate-bias controller CNT10 receives thedetected signal sig10 and supplies substrate biases vbp10 and vbn10 tothe main circuit LOG10. The substrate-bias controller CNT10 controls thesubstrate biases vbp10 and vbn10 so that the operating speed of the maincircuit LOG10 follows a change in the clock signal clk10. As a result,the operating speed of the main circuit can be changed according to theexternal clock.

[0113]FIG. 17 is a diagram showing another embodiment of the invention.A main circuit LOG20 outputs a circuit characteristics detected signalsig20. A substrate-bias controller CNT20 generates substrate biasesvbp20 and vbn20 in response to the detected signal sig20. The substratebiases vbp20 and vbn20 are supplied to both the main circuit LOG20,which has detected the characteristics and the main circuit LOG21. Withsuch a configuration, the characteristics fluctuation in the maincircuits LOG20 and LOG21 can be suppressed.

[0114]FIG. 18 is a diagram showing another embodiment of the invention.As shown in the diagram, when a plurality of main circuits LOG30 toLOG32 construct one semiconductor integrated circuit LSI30, by mountingcontrollers CNT30 to CNT32 of the embodiment for the respective maincircuits, local characteristics fluctuation in the semiconductorintegrated circuit can be suppressed, and the power control of eachlocal part can also be performed.

[0115]FIG. 2 is a diagram showing a detailed embodiment of theinvention. A clock signal clk01 from the outside is supplied to aclock-duty modulator VCLK01. On the basis of the clock signal clk01, theclock-duty modulator VCLK01 generates a clock signal clk02 of adifferent duty ratio. A delay monitoring circuit DMON01 receives theclock signal clk02 from the clock-duty modulator VCLK01 and outputs adelayed output signal inv01 which is delayed by predetermined delay. Adelay comparator CMP01 detects a phase difference, that is, a delaydifference between the clock signal clk02 from the clock-duty modulatorVCLK01 and the delayed output signal inv01 from the delay monitoringcircuit DMON01, and compares the difference with a predetermined setvalue. When the delay is advanced as compared with the predetermineddesign value, the delay comparator CMP01 outputs an up01 signal. Whenthe delay is behind, the delay comparator CMP01 outputs dw01. Asubstrate-bias generator SBG01 generates two kinds of biases: asubstrate bias vbp01 for a p-channel type MOSFET, and a substrate biasvbn01 for an n-channel type MOSFET. Each time the up01 signal isreceived from the delay comparator CMP01, the substrate-bias generatorSBG01 increases the voltage of vbp01 on a predetermined voltage unitbasis and decreases the voltage of vbn01 on a predetermined voltage unitbasis. Each time the dw01 signal is received from the delay comparatorCMP01, the substrate-bias generator SBG01 decreases the voltage of vbp01on a predetermined voltage unit basis and increases the voltage of vbn01on a predetermined voltage unit basis. The resultant substrate bias isapplied to the substrate of MOSFET of the delay monitoring circuitDMON01.

[0116] The delay monitoring circuit DMON01 is comprised of an n-channeltype MOSFET and a p-channel type MOSFET formed on the semiconductorsubstrate, and is constructed so that the substrate bias of the MOSFETis changed by the substrate bias signal from the substrate biasgenerator SBG01. As will be described hereinafter, by changing thethreshold voltage in accordance with a change in the substrate bias, thedelay is changed.

[0117] When the delay difference between the clock signal clk02 and thedelayed output signal inv01 becomes equal to the predetermined designvalue, the delay comparator CMP01 does not output the up01 and dw01signals. When no output signal is supplied from the delay comparatorCMP01, the substrate bias generator SBG01 determines that thesubstrate-bias voltage value is decided, and applies the determinedsubstrate bias to the substrate of the main circuit LOG01. Bycontrolling the substrate bias of the MOS transistor, the thresholdvoltage is controlled.

[0118] With such a construction, the threshold voltage of the MOStransistor is controlled by controlling the substrate bias, therebyenabling the operating speed to be always constant, even when theoperation environment and the like changes. With such a construction,when the main circuit is in the suspended mode, the threshold of themain circuit is increased to reduce the leakage current, therebyenabling the power consumption to be reduced.

[0119]FIG. 3 is a diagram showing an embodiment of the clock-dutymodulator. By combining a flip-flop and an AND gate, three kinds ofclocks clka, clkb, and clkc of different phases can be generated from aclock input clk11. The waveforms of the clock signals are shown in FIG.4.

[0120]FIG. 5 is a diagram showing an embodiment of the delay monitoringcircuit. The delay monitoring circuit is obtained by connectinginverters in series. The clock output clkb of the clock-duty modulatoris supplied to the inverter at the first stage. Output signals invb andinva are taken from the last stage inverter at the last stage and theinverter two stages before the last stage. The threshold of eachinverter is changed by controlling the substrate bias by the substratebias signals vbp11 and vbn11, so that the delay difference between eachof the signals inva and invb and the input signal clkb can becontrolled.

[0121]FIG. 6 is a diagram showing an embodiment of the delay comparator.The delay comparator comprises flip-flops and AND gates. The clockoutputs clka, clkb and clkc from the clock-duty modulator and the delayoutput signals inva and invb of the delay monitoring circuit arereceived and up11 and dw11 signals are outputted. When the delay of thedelay monitoring circuit is equal to the design value, an AND gateoutput and11 of inva and clkb is generated and an AND gate output and12of invb and clkb is not generated. In this case, both the up11 and dw11signals are not outputted. When the characteristics fluctuate due tocharacteristics fluctuation caused by a fabrication process or a changein the environment and the delay of the delay monitoring circuit isadvanced, the up11 signal is outputted. When the delay of the delaymonitor is behind, the dw11 signal is outputted.

[0122]FIG. 7 is a diagram showing an embodiment of the substrate-biasgenerator, which comprises an AND gate, an OR gate, a flip-flop, aselector, and a digital-to-analog converter. The flip-flops construct aregister whose output position can be changed to “up” or “down”. Only asignal in a resistor position corresponding to the desired substratebias is outputted.

[0123] In the initial state, an output signal is generated from dff15 asa central register output. The up11 signal and the dw11 signal from thedelay comparator are received and the output position of the register ischanged to “up” or “down” in accordance with the clock signal clka ofthe clock-duty modulator. A digital-to-analog converter DAC11 generatesthe substrate bias vbp11 for p-channel type MOSFET and the substratebias vbn11 for n-channel type MOSFET in accordance with the outputposition dff10 to dff19 of the register. Each time the up11 signal isreceived, the register position of the register output is changed one byone,in the direction extending from dff10 to dff19. When the dw11 signalis received, the register position of the register output is shifted oneby one in the direction from dff19 to dff10. Each time the registeroutput is shifted by the up11 signal, the substrate bias output changesthe substrate bias by 0.2V. In the case where the supply voltage is1.8V, when the supply voltages of −1.8V and 3.6V are supplied to theDAC11, the vbp11 signal is generated at the interval of 0.2V in therange from 1.8V to 3.6V and the vbn11 signal is generated at theinterval of 0.2V in the range from 0.0V to −1.8V.

[0124] When the delay of the delay monitoring circuit is advanced ascompared with the design value, the substrate-bias generator receivesthe up11 signal. Consequently, the register output increases step bystep, and the substrate bias increases 0.2V each by the vbp11 signal anddecreases 0.2V each by the vbn11 signal. By applying the resultantsubstrate bias to the MOSFET substrate of the delay monitoring circuit,the monitor delay is slowed. When the delay of the delay monitoringcircuit is behind the design value, the substrate-bias generatorreceives the dw11 signal. Consequently, the register output decreasesstep by step, and the substrate bias decreases 0.2V each by the vbp11signal and increases 0.2V each by the vbn11 signal. By applying theresultant substrate bias to the MOSFET substrate of the delay monitoringcircuit, the monitor delay is advanced.

[0125]FIGS. 8 and 9 are diagrams each specifically showing the selectorin the substrate-bias generator. On the basis of a select1 input signalof the selector, the register signal of the substrate-bias generatorswitches the up and down directions.

[0126]FIG. 19 is a diagram specifically showing the digital-to-analogconverter. Substrate biases vbp200 and vbn200 corresponding to theregister outputs dff20 to dff29 are generated.

[0127]FIG. 10 shows an embodiment of the lock detector. The substratebias output of the substrate-bias generator is always applied to theMOSFET substrate in the delay monitoring circuit. When thecharacteristics of the delay monitoring circuit fluctuate, the biasvoltage is changed by each clock until the substrate bias voltage isdetermined. In order to apply the substrate bias for controlling themain circuit after the substrate bias is determined, a lock detector maybe inserted. Outputs vbp21 and vbn21 of the digital-to-analog converterDAC21, which is directly connected to the shift register outputs dff10to dff19 in the substrate-bias generator, are connected to the MOSFETsubstrate in the delay monitoring circuit. The lock detector LCK11receives the shift register outputs dff10 to dff19 and clka, up11, anddw11 signals, detects that the substrate-bias voltage value is lockedthrough the AND gate and flip-flop, and transmits the signals to thedigital-to-analog converter DAC22. The digital-to-analog converter DAC22outputs the substrate biases vbp22 and vbn22 and controls the substratebias of the MOSFET substrate in the main circuit.

[0128]FIG. 11 shows an embodiment of a standby circuit. When the maincircuit is in the suspended mode, by maximizing the substrate bias inthe p-channel type MOSFET and by minimizing the substrate bias in then-channel type MOSFET, both the leakage current and the powerconsumption can be reduced. Substrate bias outputs vbp23 and vbn23 froma digital-to-analog converter DAC23 in the substrate-bias generator aregenerated as shown in the diagram. The source of the pMOS is connectedto the maximum substrate bias vch and the source of the nMOS isconnected to the minimum substrate bias vsl. When the supply voltage is1.8V, vch is 3.6V and vsl is −1.8V, a suspension signal stb21 and anstb20 signal having the phase opposite to that of stb21 are supplied tothe gates of the NMOS and pMOS, respectively.

[0129] Both FIGS. 13 and 14 show the relation between the substrate-biasvoltage and the threshold voltage of the MOS transistor. FIG. 13 showsthe case of the nMOS. FIG. 14 illustrates the case of the pMOS. Thethreshold of the MOS transistor changes according to the substrate biasas shown in both FIGS. 13 and 14. Consequently, when a gate like aninverter is formed by using an mMOS transistor and a pMOS transistor, asshown in FIG. 15, the larger the absolute value of the substrate biasis, the longer the delay is. Consequently, by controlling the substratebias, the delay of the CMOS circuit can be maintained to be alwaysconstant. When the characteristics of (II) are given to a CMOS circuithaving the characteristics of (I) by decreasing the thresholdpreliminarily by a process, by increasing or decreasing the bias voltagearound 1.0V of the substrate bias as a center, the operating speed canbe made faster or slower as compared with that of the initial CMOScircuit.

[0130] When no compensation is performed, the delay fluctuation in theCMOS circuit exists at about 45%. In a method of controlling the leakagecurrent to be constant, a change in temperature cannot be dealt with, sothat the fluctuation in delay becomes 60% and the range is ratherwidened. In the method of suppressing the delay fluctuation by thesupply voltage control, the range of variation is suppressed to 36%.According to the invention, the delay can be suppressed to 32%.

[0131]FIG. 21 is a diagram showing another embodiment of the invention.A delay detector MON001 receives a clock signal clk001 and outputs adelayed signal. On the basis of the delayed signal, a voltage-controlledcircuit VCNT001 generates a control signal cont001 to adigital-to-analog converter DACONV001 as, for example, a 10-bit signal.The digital-to-analog converter DACONV001 generates a substrate biasvbp001 for a pMOS transistor and a substrate bias vbn001 for an uMOStransistor in accordance with the control signal, and supplies them tothe delay detector MON001 and a main circuit LOG001. The delay detectorMON001 can change a signal transmission delay by the substrate biasesvbp001 and vbn001, and the voltage controlled circuit VCNT001 generatesa control signal so that the digital-to-analog converter DACONV001generates a substrate bias signal to make the delay in an output signalof the delay detector MON001 always constant. Consequently, theoperating speed of the delay detector MON001 and the main circuit LOG001becomes always constant.

[0132]FIG. 22 is a diagraim specifically showing an embodiment of theinvention. A delay detector MON011 is comprised of a divider DIV011 anda threshold-voltage controlled oscillator VCO011. The divider DIV011divides the frequency of a clock signal input clk011 and outputs a clocksignal clk12. The threshold-voltage controlled oscillator VCO011 canchange the oscillation frequency by substrate bias signals vbp011 andvbn011, and generates an oscillation output signal vcosig011. Avoltage-controlled circuit VCNT011 is comprised of a phase-frequencydetector PFD011 and a phase-frequency controller PFCNT011. Thephase-frequency detector PFD011 receives an output clock signal ctk012of the divider DIV011 and an oscillation output vcosig011 of thethreshold-voltage controlled oscillator VCO011, detects a frequencydifference and a phase difference between the two signals, and generatesan up signal up011 or a down signal dw011 in accordance with thedifference. The phase-frequency controller PFCNT011 converts the upsignal up011 or down signal dw011 to, for example, a 10-bit controlsignal control. A voltage generator VG011 generates a substrate biasvbp011 for the pMOS transistor and a substrate bias vbn011 for the nMOStransistor in accordance with the control signal cnt011, and suppliesthem to the substrates of the threshold-voltage controlled oscillatorVCO011 and the main circuit LOG011. A voltage-controlled circuit VCNT011controls the substrate bias, so that the output vcosig011 of thethreshold-voltage controlled oscillator VCO011 is synchronized with theoutput ctk012 of the divider DIV011 with respect to the frequency andphase. The threshold-voltage controlled oscillator VCO011 and the maincircuit LOG011 operate always at the same operating speed incorrespondence with the clock signal input clk011.

[0133]FIG. 23 is a diagram showing an embodiment of the divider. Adivider DIV012 is constructed by connecting a plurality of D-type flipflops (DFF011 and the like) as shown in the diagram. The dividergenerates an output signal clk014 by reducing the frequency of an inputclock signal clk013 by half when one D-type flip flop is used or byreducing the frequency to ¼ when two D-type flip flops are used.

[0134]FIGS. 24, 25, and 26 are diagrams showing embodiments of thethreshold-voltage controlled oscillator. The oscillation frequency ofthe threshold-voltage controlled oscillator can be varied by substratebias signals vbp012, vbp013, vbp014, vbn012, vbn013, and vbn014, andoutputs clock signals vcosig012, vcosig013, and vcosig014. VC0012 isconstructed by using inverter circuits, VC0013 is constructed by usingNAND circuits, and VC0014 is constructed by using NOR circuits.

[0135]FIGS. 27 and 28 are diagrams showing embodiments of athreshold-voltage controlled delay line. The delay comparator 5 can besimilarly constructed like VCL011 or VCL012 by using an NAND circuit oran NOR circuit.

[0136]FIG. 29 is a diagram showing an embodiment of the phase-frequencydetector. A phase-frequency detector PFD012 detects a phase differenceand a frequency difference between a clock signal clk019 and anoscillation output vcosig015. When the clock signal clk019 leads, an upsignal up012 is generated. When the oscillation output vcosig015 leads,a down signal dw012 is generated.

[0137]FIG. 30 is a diagram showing an embodiment of the phasefrequencycontroller. A phase frequency controller PFCNT012 is comprised of anup-down counter UDC011 and a decoder DEC011. When an up signal up013 isreceived, the up-down counter UDC011 increases an output signal cnt012by “1” in binary number. When a down signal is received, the up-downcounter UDC011 decreases an output signal by “1” and the result of theaddition or substraction is outputted as a control signal cnt012 ofabout 4 bits. The decoder DEC011 decodes the control signal cnt012 andgenerates a control signal cnt013 of about 8 bits.

[0138]FIG. 31 shows the configuration of the up-down counter whichcomprises D-type flip flops DFF015, DFF016, DFF017, and DFF018, T-typeflip flops TFF011, TFF012, TFF013, TFF014, TFF015, TFF016, TFF017, andTFF018, a half adder HA011, full adders FA011, FA012, and FA013, an ANDgate, a NAND gate, and an OR gate. When an up signal up014 is supplied,the counter is incremented. When a down signal dw014 is supplied, thecounter is decremented and 4-bit output signals cnt014, cnt015, cnt016,and cnt017 are outputted. By feeding back the output signals to theinside, the counting is limited. An asynchronous up-down counter can beconstructed with the configuration.

[0139] A half adder HA012 can be constructed as shown in FIG. 32. A fulladder FA014 can be constructed by combining half adders HA013 and HA014,as shown in FIG. 33.

[0140] A decoder can be constructed as shown in FIG. 34. In this case, a4-bit input signal cnt0-18-021 is converted into an 8-bit output signalcnt022-029.

[0141]FIG. 35 shows an embodiment of a voltage generator. Besides thedigital-to-analog converter shown in FIG. 19, a voltage generator VG013can be also constructed as illustrated in FIG. 35. An output voltage ischanged by control signals cnt030 to cnt037 for input. Operatingamplifier OPAMPP011 and OPAMPN011 and resistors RFP and RFN can beconnected to the output part in order to decrease output impedance.Outputs of the voltage generator VG013 become substrate bias signalsvbp018 and vbn018.

[0142]FIG. 36 is a diagram showing another embodiment of the invention.A delay detector MON012 receives a clock signal clk020 and outputs adelay signal. A voltage-controlled circuit VCNT012 generates a controlsignal on the basis of the delay signal and transmits it to adigital-to-analog converter DACONV011. The digital-to-analog converterDACONV011 generates substrate bias signals vbp019 and vbn019 inaccordance with the control signal and applies them to the delaydetector MON012. Operating amplifiers OPAMPP012 and OPAMPN012 receivethe substrate bias signals, output substrate bias signals vbp020 andvbn020 at the same voltages as vbp and vbn, and apply them to thesubstrate of a main circuit LOG012. The delay detector MON012 can changea signal transmission delay by the substrate biases vbp019 and vbn019,and the voltage-controlled circuit VCNT012 generates a control signal sothat the digital-to-analog converter generates a substrate bias signalwhich makes the delay of the output signal of the delay detector MON012always constant. Consequently, the operation speed of both the delaydetector MON012 and the main circuit LOG012 becomes always constant.When the circuit scale of the main circuit LOG012 is large, it takestime until the substrate bias signals vbp020 and vbn202 become stable.By inserting circuits of a low output impedance such as the operatingamplifiers OPAMPP012 and OPAMPN012, it hastens the stabilization of thesubstrate bias signal. The operating amplifiers may be also inserted forthe substrate biases vbp019 and vbn019 for the delay monitoring circuitMON012.

[0143]FIGS. 37 and 38 show embodiments of the operating amplifier.

[0144]FIG. 39 is a diagram showing another embodiment of the invention.A delay detector PMON041 for a pMOS transistor can change delay by asubstrate bias signal vbp041 for a PMOS transistor. A delay detectorNMON041 for an nMOS transistor can change delay by a substrate biassignal vbn041 for an NMOS transistor. The delay detectors PMON041 andNMON041 receive a clock signal clk041 and transmit a delayed signal tovoltage-controlled circuits VCNT041 and VCNT042, respectively. Each ofthe voltage-controlled circuits VCNT041 and VCNT042 outputs a controlsignal according to the delay signal. Digital-to-analog convertersDACONV041 and DACONV042 generate a substrate bias vbp041 for a pMOStransistor and a substrate bias vbn041 for an nMOS transistor inaccordance with the respective control signals, and supply them to thedelay detectors PMON041 and NMON041, respectively, and to the maincircuit LOG041. The digital-to-analog converter DACONV041 eliminates achange in delay caused by a pMOS transistor, and the digital-to-analogconverter DACONV042 eliminates a change in delay caused by an nMOStransistor, thereby keeping constant the operating speeds of the maincircuit LOG041 and the delay detectors PMON041 and NMON041. Byindependently controlling the change in delay of the pMOS transistor andthe change in delay of the nMOS transistor, the very accurate substratebias control can be realized.

[0145]FIGS. 40 and 41 show delay detectors for pMOS transistors. Withthe configurations shown in the diagrams, substrate biases vbp042 andvbp043 for pMOS transistors are supplied, thereby enabling a change indelay to be controlled.

[0146]FIGS. 42 and 43 show delay detectors for nMOS transistors.Similarly, substrate biases vbn042 and vbn043 for nMOS transistors aresupplied, thereby enabling a change in delay to be controlled.

[0147]FIG. 44 is a diagram showing another embodiment of the invention,which comprises the delay controller according to the embodiment of FIG.2 and a leakage-current detector LMT051. The leakage-current detectorreceives substrate biases vbp051 and vbn051, generated by a substratebias generator SBG051, and detects a leakage current of the circuit.When the leakage current increases to a predetermined value or more, thesubstrate bias control is stopped so that the substrate bias does notchange. The leakage-current detector LMT051 therefore limits theincrease in the leakage current by the substrate bias control, therebypreventing an erroneous operation caused by an operating error in hightemperature or the like.

[0148]FIG. 45 is a diagram showing another embodiment of the invention,which comprises the delay controller in the embodiment of FIG. 22 and aleakage-current detector LMT052. The leakage-current detector receivessubstrate biases vbp052 and vbn052, generated by a voltage generatorVG051, and detects a leakage current of the circuit. When the leakagecurrent increases to a predetermined value or more, the substrate biascontrol is stopped so that the substrate bias does not change. Theleakage-current detector LMT052 therefore limits the increase in theleakage current by the substrate bias control, thereby preventing anerroneous operation caused by an operating error in high temperature orthe like.

[0149]FIG. 46 is a diagram showing an embodiment of the leakage currentdetector, which is inserted between up signals up055 and up056 in thedirection of increasing a leakage current by the substrate bias control.The limit value of the leakage current by the substrate bias vbp053 fora pMOS transistor is determined by a diffusion-layer width wn01 of annMOS transistor. The limit value of the leakage current by the substratebias vbn053 for an nMOS transistor is determined by a diffusion-layerwidth wp01 of a pMOS transistor.

[0150]FIG. 47 is a diagram showing a method of applying the proposedtechnique. A standard CMOS device has distribution of performance asshown in FIG. 47(a) by the factors such as fabrication process,operating voltage, and operating temperature. The threshold upper limitof the distribution is determined by the lower-bound of delay and thelower limit is determined by the upper-bound of power consumption. Whenthe proposed technique is applied to such a device, the spread of theperformance distribution can be narrowed, as shown by the hatched part.In the case of applying the substrate bias only in the reverse biasdirection, with respect to the control by the substrate bias, thedistribution is shifted to the side where the threshold is high and theoperation speed is slow. When the device is fabricated preliminarilywith a lower threshold, as shown in FIG. 47(b), the lower limit of thedistribution exceeds the limit of power consumption. When the proposedtechnique is applied to the device, however, the distribution shown bythe hatched part can be obtained. The distribution of the device can beset in an area where the threshold is low and the operation speed ishigh without exceeding the limit of power consumption, so that thehigh-processing speed of the circuit can be realized.

[0151]FIG. 48 is a diagram showing another method of applying theproposed technique. As shown in FIG. 50, the substrate bias of up toabout 0.5V can be applied in the forward bias direction to operate adevice. When the proposed technique is applied by performing the forwardbias control, as shown in FIG. 48, the distribution of a standard CMOSdevice can be converged to the hatched position, in which the thresholdis low and the operation is high. Thus, the high-processing speed of thecircuit can be realized.

[0152]FIG. 49 is a diagram showing another method of applying theproposed technique. When the substrate bias control in both the reversebias direction and the forward-bias direction are used, the distributionof the device can be set to the design center value, as shown by thehatched distribution. The yield of the device can therefore betherefore.

[0153]FIG. 51 is a diagram showing another embodiment of the invention,which comprises the delay controller according to the embodiment of FIG.44 or 45, a substrate-bias stable-state detector VSTS061, asupply-voltage stable-state detector VSTD061, a lock detector LDT061, areset cancellation circuit RCN061, and a standby circuit STB061. By theembodiment, the operation procedure of the semiconductor integratedcircuit according to the invention, is determined. When the power switchis turned on, the substrate bias is supplied, and the substrate-biasstable-state detector VSTS061 determines the stable state of thesubstrate bias potential and generates a substrate-bias stable-statesignal vbst061. Upon receipt of the substrate-bias stable-state signalvbst061, the supply-voltage stable-state detector VSTD061 supplies avoltage, determines the stable state of the supply voltage, andgenerates a supply-voltage stable-state signal vdst061. By thisprocedure, the substrate bias is always supplied before the supplyvoltage, thereby enabling prevention of latch-up of the MOS transistor.When the supply-voltage stable-state signal vdst061 is supplied, a clocksignal clk061 starts to be transmitted to the controller. The lockdetector LDT061 receives a clock signal clk062 supplied to thecontroller, an up signal up062 and a down signal dw061 which are in thecontroller. When the control signal in the controller becomes stable,the lock detector LDT061 outputs a lock signal lck061. The resetcancellation circuit RCN061 receives the lock signal lck061 and thesupply-voltage stable-state signal, vdst061 and outputs a resetcancellation signal rst061. The main circuit LOG061 cancels the resetstate by receiving the reset cancellation signal rst061 and startsoperating. By the procedure, an erroneous operation of the main circuitLOG061 is prevented.

[0154] The operation procedure of the invention according to theembodiment is shown in FIGS. 56 and 57.

[0155]FIG. 56 is a diagram showing the processing procedure from thestart of the system until the start of the operation of the maincircuit. Such a procedure can be made by a program or made as a wiredROM.

[0156] After the start of the system in process fcl, the maximum voltageis applied as a pMOS substrate bias Vbp and the minimum voltage isapplied as an nMOS substrate bias Vbn as shown in process fc2. Inprocess fc3, whether the substrate bias is stable or not is determined.The system waits until the substrate bias becomes stable. Afterobtaining the stable state, the program moves to process fc4. After thesubstrate bias is stabilized, a supply voltage is supplied in processfc4. In process fc5, whether the supply voltage is stable or not isdetermined. The system waits until the supply voltage becomes stable.After obtaining the stable state, the program moves to process fc6. Inprocess fc6, the substrate bias control is started, and whether thecontrol signal is locked or not is determined. When the control signalis not locked, a leakage current monitor checks whether the leakagecurrent exceeds the limit or not in process fc7. When NO, the programcontinues process fc6. When the leakage current exceeds the limit inprocess fc7, a limiter of the leakage current operates in process fc8,so that the substrate bias control signal does not change any more, andthe program progresses to process fc9. When the substrate bias controlsignal is locked within the limit of the leakage current, the programshifts from process fc6 to process fc9. In process fc9, the reset iscancelled and the operation of the main circuit is started. By thisoperating procedure, the latch-up of the MOS transistor at the operationstart time and an erroneous operation of the circuit, caused by theoperating error in high temperature or the like, can be prevented.

[0157]FIG. 57 is a diagram showing a procedure of preventing anerroneous operation caused by an operating error in high temperature orthe like during the operation of the main circuit. The reset iscancelled and the operation of the main circuit is started in processfc11. After that, it is confirmed in process fc12 that the substratebias control signal is always locked. When it is locked, whether astandby signal is generated or not is determined in process fc15. Whenthe standby signal is not generated, the program returns to processfc12. When the substrate bias signal is unlocked in process fc12, theleakage current monitor determined the limit of the leakage current inprocess fc13. When the leakage current does not exceed the limit, theprogram returns to process fc12. When the leakage current exceeds thelimit, the limiter is operated in process fc14 to stop a change in thesubstrate bias control signal, and the program progresses to processfc15. When a standby signal is generated in process fc15, the pMOSsubstrate bias Vbp is increased to the maximum value and the nMOSsubstrate bias is decreased to the minimum value in process fc16,thereby reducing the power consumption by the leakage current in thestandby state.

[0158] In process fc17, generation of an active signal is detected.Until it is generated, the standby state is maintained. When the activesignal is generated, the standby state is cancelled to thereby restartthe operation of the main circuit, and the program returns to processfc12.

[0159]FIG. 52 is a diagram showing an embodiment of the substrate-biasstable-state detector. When a reset switch RSTS061 is cancelled, thesubstrate bias voltage is charged in a capacitor C061 through a resistorR061. Vbp062 denotes a power source. When the charged voltage exceeds apredetermined value, buffer circuits BUF061 and BUF062 operate, and asubstrate-bias stable-state signal vbst062 is generated.

[0160]FIG. 53 is a diagram showing an embodiment of the supply-voltagestable-state detector. When a substrate-bias stable-state signal vbst063is received, an n-type MOS transistor is turned off and the supplyvoltage is charged in a capacitor C062 through a resistor R062. When thecharged voltage exceeds a predetermined value, buffer circuits BUF063and BUG064 operate, and a power supply stable-state signal vdst062 isgenerated.

[0161]FIG. 54 is a diagram showing an embodiment of the lock detector.The frequency of a clock signal clk063 is divided by a divider DIV061,and a resultant signal is supplied as a clock signal to a D-type flipflop DFF061. The NOR of an up signal up063 and a down signal dw063 isobtained and is supplied as a data signal to DFF061. When both the upsignal and the down signal are not generated, a lock signal lck062 isgenerated.

[0162]FIG. 55 is a diagram showing an embodiment of the resetcancellation circuit. A reset cancellation circuit RCN062 receives alock signal lck063 and a supply-voltage stable-state signal vdst063, andgenerates a reset cancellation signal rst062. In the state where noinput signal is supplied before the start of the operation of the systemand the state where only the supply-voltage stable-state signal vdst063is generated, the reset cancellation signal rst062 is at the low levelto maintain the reset state. After that, when the lock signal lck063 isgenerated, rst062 goes high and the reset is cancelled. Once the resetis cancelled, the reset cancellation signal rst062 maintains at the highlevel and is not reset until the system is stopped.

[0163]FIG. 58 is a diagram showing another embodiment of the invention.By adjusting the operating speed of an input/output circuit 1O071 byusing a substrate bias signal vbb071 for speed control outputted from aspeed controller DCNT071, the signal transmitting speed of both aninput/output signal sig071 from the outside to the input/output circuitIO071, and a signal sig072 from the input/output circuit IO071 to a maincircuit LOG071, is controlled. The signal transmitting speed of thesignal to the input/output circuit IO071 may vary according to thevoltage. By keeping the speed at the rising edge and the speed at thetrailing edge in the signal transition of IO071 at a constant value, thespeed variation can be eliminated.

[0164] Another feature of the embodiment is that the operating speed ofthe input/output circuit can be controlled independent of the maincircuit. When the operating speed of an external circuit is slow, it isirrelevant that the input/output circuit operates at a faster rate. Thesubstrate bias of the input/output circuit is controlled separately fromthe main circuit. The threshold of a transistor constructing this partis set to be high, and the power consumption by the leakage current canbe reduced instead of regulating the operating speed.

[0165]FIG. 59 is a diagram showing another embodiment of the invention.A clock generator CPG081 can vary the frequency of a clock signal clk081in accordance with a control signal cnt081. A speed controller DCNT081generates a substrate bias control signal vbb081 according to thefrequency of the clock signal clk081 and supplies it to a main circuitLOG081. Consequently, the main circuit LOG081, can operate at an optimumspeed for a change in the clock signal clk081 generated by the clockgenerator CPG081. In a signal process performed by the main circuitLOG081, the processing speed and performance required vary according tothe purpose of use, as shown in FIG. 60. By changing the operating speedin accordance with the purpose of use, the power consumption can bereduced.

[0166]FIG. 61 is a diagram showing another embodiment of the invention.The frequency of a clock signal clk091 generated by a clock generatorCPG091 is divided by dividers DIV091, DIV092, DIV093, and the like,thereby generating clock signals clk092, clk093, and clk094 of differentfrequencies. Speed controllers DCNT091, DCNT092, and DCNT093 receive theclock signals clk092, clk093, and clk094, and generate optimum substratebias signals vbb091, vbb092, and vbb093 according to the respectiveclock frequencies to control the operating speeds of main circuitsLOG091, LOG092, and LOG093. Thus, in one system, blocks pertaining torelated processes can operate at different processing speeds.

[0167]FIG. 65 shows an embodiment of divided blocks in a system. Forexample, the processing speed of a block of a liquid-crystal displaycontroller LCD can be varied according to the resolution of aliquid-crystal display. By properly adjusting the operating state(active state) or the non-operating state (standby state) of each block,the power consumption can be reduced.

[0168]FIG. 62 is a diagram showing another embodiment of the invention.Speed controllers DCNT101, DCNT102, and DCNT103 which receive a clocksignal clk101 of a clock generator CPG101, generate substrate-biassignals vbb101, vbb102, and vbb103 in accordance with supply voltagesvdd101, vdd102, and vdd103 and apply them to main circuits LOG101,LOG102, and LOG103, respectively. Since the supply voltages vdd101,vdd102, and vdd103 which are different from each other, are applied, themain circuits LOG101, LOG102, and LOG103 can operate by receivingsubstrate biases which are optimum to the respective operating speeds.In the case of applying different supply voltages to blocks, each forrelated processes within one system, the optimum substrate bias controlcan be performed to each of the main circuits constructing the blocks.

[0169]FIG. 63 shows a developed example of FIG. 62. As illustrated inFIG. 63, by providing switch MOSS SW104, SW105, and SW106 to maincircuits, and turning them off at the time of standby or the like, thepower of each block can be further reduced. When it is designed so thatthe leakage current of an FET as a switch is smaller than the sum of theleakage the currents of FETs in a block, the effect of reduction in theleakage current in the standby mode or the like can be obtained. Forexample, the switch can be constructed by an MOSFET having a highthreshold.

[0170]FIG. 64 is a diagram showing another embodiment of the invention.In a main circuit LOG111 representing one of a plurality of blocksprovided for related processes, by laying out a speed controllerDCNT111, especially, a delay detector MON111 to be in the center of theblock, the delay detector MON111 can be designed so as to represent theoperating characteristics of the block.

[0171]FIG. 66 is a diagram showing another embodiment of the invention.In a main circuit LOG121, a delay detector MON121 and avoltage-controlled circuit VCNT121 in a speed controller are formed. Adigital-to-analog converter DACONV121 for generating a control voltagecan be fabricated on a different chip. Consequently, the number ofcircuits in the speed controller, which have to be formed in the maincircuit, is decreased, thereby enabling the area and-the powerconsumption to be reduced.

Industrial Applicability

[0172] As described above, according to the invention, by controllingthe threshold of an MOS transistor constructing a circuit, thecharacteristics fluctuation of a CMOS circuit is suppressed so that theoperating speed can be improved. By preliminarily setting the thresholdof the MOS transistor to a low value in a process, the improvement inspeed becomes more effective. In order to digitally detect thecharacteristics fluctuation amount, the control circuit takes the formof a digital circuit so that the time of stabilizing the control signalcan be shortened. Since the control circuit can be formed in a smallcircuit scale, a plurality of control circuits can be arranged within asemiconductor integrated circuit whose threshold has to be controlled,and a local characteristics fluctuation can be suppressed. Further, thelocal power control in the semiconductor integrated circuit can berealized.

1. A semiconductor integrated circuit device comprising a logic circuitto perform a predetermined process, a clock generator to supply a clocksignal to the logic circuit, and a speed controller to control operatingspeed of the logic circuit, characterized in that the clock generatorchanges the frequency of the clock signal by a frequency control signalduring a time when the logic circuit is operating, and the speedcontroller controls the operating speed of the logic circuit inaccordance with a change in the clock signal.
 2. A semiconductorintegrated circuit device comprising a logic circuit having at leastfirst and second blocks, first and second speed controllers, and a clockgenerator, characterized in that clock signals of different frequenciesare supplied to the first and second blocks, and the first and secondspeed controllers control the operating speeds of the logic circuit inthe blocks in accordance with the clock signals supplied to therespective blocks.
 3. A semiconductor integrated circuit devicecomprising a logic circuit having at least first and second blocks,first and second speed controllers, and a clock generator, characterizedin that different supply voltages are supplied to the first and secondblocks, and the first and second speed controllers control operatingspeeds of the logic circuit in the blocks in accordance with the supplyvoltages supplied to the respective blocks.
 4. A semiconductorintegrated circuit device comprising a logic circuit having at leastfirst and second blocks and first and second speed controllers,characterized in that at least one of the first and second speedcontrollers is comprised of a delay detector and a controller, and thedelay detector is disposed in the center of the corresponding first orsecond block.